Cadence Central

maintained by 

The Cadence toolset is a complete microchip EDA system, which is intended to develop professional, full-scale, mixed-signal microchips and breadboards.  The modules included in the toolset are for schematic entry, design simulation, data analysis, physical layout, and final verification.  The Cadence tools at Ohio State are the same as those at most every professional mixed-signal microelectronics company in the United States.  The strength of the Cadence tools is in its analog design/simulation/layout and mixed-signal verification and is often used in tandem with other tools for RF and/or digital design/simulation/layout, where complete top-level verification is done in the Cadence tools.

Another important concept is that the Cadence tools only provide a framework for doing design.  Without a foundry-provided design kit, no design can be done.  Hence, provided below are instructions on how to setup an OSU EE HP account for using Cadence tools, then below that are instructions are how to setup various design kits presently on the HP system.  We recommend that every user: setup the base Cadence tools, then setup the NCSU Cadence design kit (CDK) for the MOSIS SCMOS processes under the ICFB (Integrated Circuit Front to Back) tools. [Front end design refers to schematic design and simulation, while back refers to layout and fabrication implementation.]

It is not necessary to install any of the other design kits, although users may want to setup the AMS CSX design kit separately if they would like to go through the ee323 Cadence tutorial examples written by J. Zohios.  Also, we strongly recommend using the directory structures/names presented in the Cadence setup instructions below.  Further, do not run ICFB in your root directory; the files that are created by one design kit can interfere with other ones.

Please email any questions on the Cadence setup instructions provided on this page to I.E. Group.

Please consider signing up for the EDA users mailing list for Cadence (and other EDA tools') configuration updates and additional resources for non-trivial tool questions [Note: mises@ee mailing list members are already subscribed].

The Cadence Disclaimer:

Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment.

• Cadence Links
• Cadence Design Systems
• North Carolina State University MOSIS Process Cadence Design Kit
• NCSU Cadence Page
• MOSIS Educational Program
• MOSIS SCMOS Design Rules
• MOSIS Fabrication Schedule
• MOSIS Educational Program
• MOSIS Educational Program Enrollment Form
• MOSIS Educational Program Report Submission Form
• MOSIS Wafer Electrical Test Data and SPICE Model Parameters
• MOSIS Web-based Status Forms
• Listing of Other Unversity Cadence Pages
• Learning about Cadence Products
• For new users and class project users
• Some Cadence Tutorials
• Some LVS tips for the new user
• Top level integration recommendations and class project requirements
• Some general hints & tips for the amateur user
• For mixed-signal simulation work
• Some notes on mixed signal simulation basics in Cadence
• Some notes on the Hierarchy Editor in Cadence
• For digital design work
• HDL synthesis tutorial using BuildGates Extreme.
• Automatic Place & Route Tutorial using Silicon Ensemble.
• A tutorial to automatically generate a layout from a Cadence digital schematic for the EE environment [in case your digital design is in schematic form, instead of in a hardware description language (HDL)...]
• Cadence Toolset Setup
1. To use Cadence, make a cadence directory (~/cadence/)
mkdir ~/cadence
2. Then source the ER4 system Cadence ICFB configuration file.
source /opt/local/cadence/Startup.EE
3. To run generic Cadence ICFB (Virtuoso Toolset) at the command line, use the following commands in the cadence directory (Note: Without a process design kit, no simulation or layout can be done, so running ICFB is pointless until a design kit has been setup):
source /opt/local/cadence/Startup.EE
icfb &
4. Please email any questions on the Cadence setup instructions provided on this page to I.E. Group.
• Cadence Design Kit for the MOSIS SCMOS processes (Cadence ICFB) developed by NCSU primarily with additional resources from OSU, VT, UT, and IIT
1. Make a subdirectory for work using the NCSU CDK (~/cadence/NCSU/)
mkdir ~/cadence/NCSU
2. Then copy all of the NCSU CDK user files and the ER4 ICFB and MGC Artist Link configuration file into this NCSU work directory. [Note: you will want to make symbolic links for the '.cdsinit' file, the 'config_ncsu_current' file, and the 'config_icfb' file, so that your configurations will always be up-to-date; the 'cds.lib' file will be modified, so you will need your own copy.]
ln -s /opt/local/cadence/Startup.EE ~/cadence/NCSU/config_icfb
ln -s /opt/local/cadence/design_kits/ANACAD/artist_link/current/cdsLibMgr.il ~/cadence/NCSU/.
cp /opt/local/cadence/design_kits/NCSU/current/local/user_files/cds.lib ~/cadence/NCSU/.
ln -s /opt/local/cadence/design_kits/NCSU/current/local/user_files/.cdsinit ~/cadence/NCSU/.
ln -s /opt/local/cadence/design_kits/NCSU/current/local/user_files/config_ncsu_current ~/cadence/NCSU/config_ncsu
3. To run ICFB at the command line in the NCSU work directory (~/cadence/NCSU/), use the following command:
source config_icfb
source config_ncsu
icfb &
4. Under the LIBRARY MANAGER tool, click File -> New -> Library to create a new library for designs (schematic, simulation, layout).
• Each process will require a separate design library, because process-specific parameters are bound to the schematics and layout.
• Each design library should reflect the user's name (in some form) as well as the process being used (i.e. fisherj_ami06).
• Each design library must be attached to a technology file.
• The foundy-process-size_TechLib library is the technology file to which the design library should be attached for the given foundry process.
5. EDA design kits are much like device models, in that they are never perfectly accurate and always continually growing. If you are doing research involving microchip design, you will want your CDK to be as up-to-date & advanced as possible and should use the following commands for the 'beta' version of the NCSU CDK. This version is not an 'alpha' version and has been tested for stability. Plus, the most advanced, time-saving tools that we can find are provided in this CDK. If time and accuracy are important to your research, use the 'beta' version.
   rm ~/cadence/NCSU/.cdsinit
   rm ~/cadence/NCSU/config_ncsu
   ln -s /opt/local/cadence/design_kits/NCSU/beta/local/user_files/.cdsinit ~/cadence/NCSU/.
   ln -s /opt/local/cadence/design_kits/NCSU/beta/local/user_files/config_ncsu_beta ~/cadence/NCSU/config_ncsu
• AMS Design Kit for the 0.35um CSX process (Cadence ICFB)
1. Make a subdirectory for work using the AMS CDK (~/cadence/AMS_CSX/)
mkdir ~/cadence/AMS_CSX
2. Then copy all of the AMS CDK user files and the ER4 ICFB configuration file into this AMS CSX work directory. [Note: you may wish to make symbolic links for the 'config_ams' file and the 'config_icfb' file, so that your configurations will always be up-to-date.]
ln -s /opt/local/cadence/Startup.EE ~/cadence/AMS_CSX/config_icfb
ln -s /opt/local/cadence/design_kits/AMS/current/user_files/config_ams ~/cadence/AMS_CSX/.
3. To run ICFB at the command line in the AMS CSX work directory (~/cadence/AMS_CSX/), use the following commands:
source config_icfb
source config_ams
ams_cds -tech csx -tool artist -mode fb &
4. Under the LIBRARY MANAGER tool, click File -> New -> Library to create a new library for designs (schematic, simulation, layout).
• Each process will require a separate design library, because process-specific parameters are bound to the schematics and layout.
• Each design library should reflect the user's name (in some form) as well as the process being used (i.e. fisherj_amscsx).
• Each design library must be attached to a technology file.
• TECH_CSD is the technology file directory to which each design library should be attached for the AMS CSX process.
• Design Kit for MITLL AST 0.18um FDSOI CMOS process (Cadence ICFB)
1. Make a subdirectory for work using the AMS CDK (~/cadence/mitllfdsoi0p18um/)
mkdir ~/cadence/mitllfdsoi0p18um
2. Then copy all of the mitllfdsoi0p18um CDK user files and the ER4 ICFB configuration file into this mitllfdsoi0p18um work directory. [Note: you may wish to make symbolic links for the '.cdsinit' file, the 'config_mitllfdsoi0p18um' file, and the 'config_icfb' file, so that your configurations will always be up-to-date; the 'local.il' file is for your customizations you may want, and the 'cds.lib' file will be modified, so you will need your own copies.]
ln -s /opt/local/cadence/Startup.EE ~/cadence/mitllfdsoi0p18um/config_icfb
cp /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p18um/current/user_files/cds.lib ~/cadence/mitllfdsoi0p18um/.
ln -s /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p18um/current/user_files/.cdsinit ~/cadence/mitllfdsoi0p18um/.
cp /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p18um/current/user_files/local.il ~/cadence/mitllfdsoi0p18um/.
ln -s /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p18um/current/user_files/config_mitllfdsoi0p18 ~/cadence/mitllfdsoi0p18um/.
3. To run ICFB at the command line in the mitllfdsoi0p18um work directory (~/cadence/mitllfdsoi0p18um/), use the following  commands:
source config_icfb
source config_mitllfdsoi0p18
icfb &
4. Under the LIBRARY MANAGER tool, click File -> New -> Library to create a new library for designs (schematic, simulation, layout).
• Each process will require a separate design library, because process-specific parameters are bound to the schematics and layout.
• Each design library should reflect the user's name (in some form) as well as the process being used (i.e. fisherj_mitllfdsoi0p18um).
• Each design library must be attached to a technology file.
• TECHLIB is the technology file directory to which each design library should be attached for the mitllfdsoi0p18um process.
• Design Kit for MITLL AST FDSOI 0.25um CMOS process (Cadence ICFB)
1. Make a subdirectory for work using the AMS CDK (~/cadence/mitllfdsoi0p25um/)
mkdir ~/cadence/mitllfdsoi0p25um
2. Then copy all of the mitllfdsoi0p25um CDK user files and the ER4 ICFB configuration file into this mitllfdsoi0p25um work directory. [Note: you may wish to make symbolic links for the '.cdsinit' file, the 'config_mitllfdsoi0p25um' file, and the 'config_icfb' file, so that your configurations will always be up-to-date; the 'local.il' file is for your customizations you may want, and the 'cds.lib' file will be modified, so you will need your own copies.]
ln -s /opt/local/cadence/Startup.EE ~/cadence/mitllfdsoi0p25um/config_icfb
cp /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p25um/current/user_files/cds.lib ~/cadence/mitllfdsoi0p25um/.
ln -s /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p25um/current/user_files/.cdsinit ~/cadence/mitllfdsoi0p25um/.
cp /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p25um/current/user_files/local.il ~/cadence/mitllfdsoi0p25um/.
ln -s /opt/local/cadence/design_kits/MITLL/mitllfdsoi0p25um/current/user_files/config_mitllfdsoi0p25 ~/cadence/mitllfdsoi0p25um/.
3. To run ICFB at the command line in the mitllfdsoi0p25um work directory (~/cadence/mitllfdsoi0p25um/), use the following  commands:
source config_icfb
source config_mitllfdsoi0p25
icfb &
4. Under the LIBRARY MANAGER tool, click File -> New -> Library to create a new library for designs (schematic, simulation, layout).
• Each process will require a separate design library, because process-specific parameters are bound to the schematics and layout.
• Each design library should reflect the user's name (in some form) as well as the process being used (i.e. fisherj_mitllfdsoi0p25um).
• Each design library must be attached to a technology file.
• LVASOI1_TechLib is the technology file directory to which each design library should be attached for the mitllfdsoi0p25um process.

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134.