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BuildGates Extreme Synthesis Tutorial



This tutorial will take a sample VHDL design and synthesize it into a Verilog netlist using BuildGates Extreme. This Verilog netlist can then be automatically placed-and-routed into a semiconductor layout using Silicon Ensemble, as seen in this tutorial.

  1. Get Sample Design and Libraries
    Sample Design: miniUART
    Universal Asynchronous Receiver-Transmitter
    VHDL Files:
    miniUART.vhd
    RxUnit.vhd
    TxUnit.vhd
    clkUnit.vhd

    Target Technology: OSU_digital_ami05
    Files needed for synthesis:
    OSU_digital_ami05.alf. Standard Cell Synthesis Library.
    OSU_digital_ami05.sym. Graphical Symbol Library For Standard Cells.

  2. Start BuildGates. Source the BuildGates startup information at the UNIX command line:

    source /opt/local/cadence/StartupSPR.EE

    Then start BuildGates using the command:

    bgx_shell -gui &

  3. Import VHDL Design. Select File -> Open and select the file type: VHDL. Select the files:
    miniUART.vhd
    RxUnit.vhd
    TxUnit.vhd
    clkUnit.vhd

    and click "OK." The command line equivalent for doing these operations would be:

    read_vhdl /rcc4/student/copusj/flow_tutorial/RxUnit.vhd
    read_vhdl /rcc4/student/copusj/flow_tutorial/TxUnit.vhd
    read_vhdl /rcc4/student/copusj/flow_tutorial/clkUnit.vhd
    read_vhdl /rcc4/student/copusj/flow_tutorial/miniUART.vhd

  4. Synthesize Design. To synthesize the imported design, select Commands -> Build_Generic. The default options should be fine for this tutorial, so click "OK." The command line equivalent of this action is:

    do_build_generic

    You can view the schematic at this point by right-clicking "miniUART" in the Logical Tab and selecting Open Schematic -> Main Window.

  5. Optimize and Map to Desired Library. The synthesized schematic uses generic logic functions and gates. The design must be mapped to a physical standard cell library and the design optimize for that library. First, open the standard cell library synthesis library file by selecting File -> Open and select the File Type: ALF library. Then, browse to the proper directory and select OSU_digital_ami05.alf and click "OK". The command line equivalent of this action is:

    read_alf OSU_digital_ami05.alf

    To map the design to the library and perform optimization, select Commands -> Set Target Technology and select OSU_digital_ami05. Then click "OK". Next, select Commands -> Optimize and select Priority Area and click "OK". This option will try to minimize the cell area of the synthesized design. The command line equivalent of this operation is:

    do_optimize -priority area

    Due to a bug in the GUI for BuildGates, the command line might have to be used to perform this operation.
  6. Save as Verilog Netlist. To save the final design as a Verilog netlist, which can later be used for Place-and-Route, select File -> Save As, the select Verilog. Enter the file name and click "OK." The command line equivalent is:

    command line equivalent: write_verilog miniUART_built.v

A final note: This whole process can be scripted in a .tcl file using the commands explained above:

read_alf OSU_digital_ami05.alf
set_global hdl_vhdl_environment common

read_vhdl RxUnit.vhd
read_vhdl TxUnit.vhd
read_vhdl clkUnit.vhd
read_vhdl miniUART.vhd

do_build_generic
do_optimize -priority area
write_verilog -hierarchical miniUART_built.v

Then, run bgx_shell filename.tcl to synthesize the circuit.
If you have any comments, suggestions, or corrections, please email I.E. Group
IE logos by Ben McCrea.
James Copus 2003