| | Standard Course Syllabus | Course Supervisor | Date of Approval |
| | Dept. of Electrical and Computer Engineering | Orin | 5/05 |
| | 561 | Digital Circuit Design |
| | 2. | CATALOG DESCRIPTION |
| | An introduction to digital circuit design using integrated circuit components; gates, counters, latches, ALU, shift registers, |
| | multiplexers, memories, etc. |
| | Quarters of Offering | Credits | | Level | Class Meeting |
| | Au, Wi, Sp Qtrs. | 3 | U G | 3 cl. |
| | Course Prerequisites |
| | Prereq: 206, 261, and prereq or concur: 320 or 323. |
| | 3. | PREREQUISITES BY TOPIC |
| | Number systems and codes, combinational logic circuits, Boolean algebra, Karnaugh maps, computer addition, flip-flops and |
| | latches, sequential circuits, registers and counters, basic digital electronics. |
| | Courses that require this as a direct prerequisite |
| | 662, 667, 762, 766, 769 |
| | 4. | Text(s) and Other Course Materials | Author(s) | Publisher |
| | Digital Design Principles and Practices, 4th Ed. | Wakerly | Prentice-Hall |
| | ISBN: 0-131-86389-4 |
| | References (supplemental reading) |
| | none |
| | 5. | COURSE OBJECTIVES |
| | 1. Students will learn digital design principles and practice. Design is based on standard MSI and LSI devices or equivalent |
| | building blocks such as counters, shift registers, and adders. The design of clocked sequential circuits based on a System |
| | Controller concept and with many inputs, some of which may be asynchronous, is emphasized. Also emphasized is a |
| | detailed analysis of the timing at each step of the design. VHDL is introduced in the course. (Criteria 3(a),(c),(e)) |
| | 2. Students will design and simulate digital circuits using a state-of-the-art CAD package. Both schematic and VHDL-based |
| | design is supported. (Criteria 3(k)) |
| | 6. | TOPICS AND (# OF LECTURES) |
| | Clocked synchronous state-machine analysis and timing (3) |
| | Analysis of sequential circuits with MSI and System Controller (5) |
| | Clocked synchronous state-machine design (4) |
| | Design with counters, shift registers, multiplexers, comparators, decoders, and adders (6) |
| | Design with asynchronous inputs and for glitch-free outputs (1) |
| | System Controller design (4) |
| | VHDL for combinational logic and state machine design (4) |
| | Logic implementation with PLDs, FPGAs, and ROMs (3) |
| | 7. | CLASS MEETING PATTERN | (For example, "3cl." means 3 48-min classes per week.) |
| | 3 cl. |
| | Thursday, August 14, 2008 09:17 AM |
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